1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of testing and monitoring leakage current on DRAM devices.
2. Description of the Prior Art
The functions that are performed by data processing systems can broadly be divided into the function of manipulating data, the logic function, and the function of retaining or storing data, the memory function. While these functions can at times be encountered on one and the same semiconductor chip, these function are in most cases provided by chips that are specifically dedicated to either one or to the other function.
This leads to the requirement that the logic chips and the memory chips must be interconnected since both types of chips are typically functionally dependent. This interconnect can degrade overall system performance and can bring with it problems of propagation delays of the electrical signals, electrical cross talk, interconnect line resistivity and others.
Continuous emphasis on improved performance of semiconductor devices has over the years resulted in a continuation of decreasing device features and increasing circuit density. Instrumental in this trend have been improvements in photolithographic techniques (allowing for reductions of device features and reductions in interconnect metal lines) and the increased use of self-aligning processing steps. These trends have led to device features in present designs that are in the sub-micron range.
The most widely used device that is used as a data storage or memory device is the Dynamic Random Access Memory (DRAM) chip. A single DRAM cell stores a bit of data on a capacitor as an electrical charge and typically consists of a single Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for data access and a single capacitor for data storage. The above-indicated reduction in device feature size results, for the DRAM cell, in serious limitations to increased data storage capability. The process technology in the manufacturing of Dynamic Random Access Memory (DRAM) has, during the last several decades, migrated from 0.8 um 4M memories to 0.18 um 256M memories with a continuing decrease in memory cell size and concurrent increase in memory capacity. This scaling down in memory cell capacity puts increased emphasis on the cell""s leakage current to maintain data retention capability.
One of the process technologies that have been used in the manufacturing of DRAM devices is the process of Selective Epitaxial Growth (SEG) of silicon. This process allows the deposition of a silicon epitaxial layer on a bare silicon surface without the simultaneous growth of amorphous silicon thin film on the silicon dioxide or silicon nitride interface. The SEG process has been used to develop an epitaxy-over-trench (EOT) process for DRAM technology. This approach allows the transfer transistor to be fabricated directly over the storage capacitor, resulting in a high density DRAM.
DRAM memory is so named because its cells can retain information only for a limited period of time before they must be read and refreshed at periodic intervals. A DRAM cell consists of one transistor and one storage capacitor. For bit densities of up to one megabit, planar-type storage capacitors are used. However, as storage densities increase, the amount of charges needed for a sufficient noise margin remains fixed. Therefore, in order to increase the specific capacitance, two different routes have been taken. The first solution is to store charges vertically in a trench. The second solution, which allows the cell to shrink in size without losing storage capacity, is to stack the capacitor on top of the access transistor. It is apparent from this that, as the memory density increases, the capacitor structure becomes more intricate and growth in the vertical direction.
DRAM storage cell capacity can be increased by making the capacitor dielectric thinner, by using a dielectric with a larger dielectric constant or by increasing the area of the capacitor. The first two options are not currently available since capacitor dielectrics thinner than those now being used in DRAM cells will suffer leakage due to an electron tunneling effect. The application of high dielectric-constant insulators other than SiO2 and Si3N4 in DRAM cells has not yet matured for mass production.
It must also be noted that since the 256-kbit DRAM generation bi-layer films (consisting of both silicon nitride and SiO2) have been used as the capacitor dielectric to increase cell capacitance. The higher dielectric constant Of Si3Ni4 (twice as large as that of SiO2) was responsible for this increase.
The approach of storing charges vertically in a trench results in stacking the storage capacitor on top of the access transistor. The lower electrode of the stacked capacitor (STC) is in contact with the drain of the access transistor whereby the bit line runs over the top of the stacked capacitor. For STC cells to be made feasible for larger capacity DRAM""s, an insulator with a larger dielectric constant than that of SiO2 must be used.
For many manufacturers, dynamic random access memories (DRAM""s) are the circuits which have the highest density and smallest feature size. However, the capacitance of a DRAM cannot be scaled at the same rate at which other circuit features are scaled back, beyond a certain point. One way therefore to maintain constant capacitance with decreasing feature size is to reduce the thickness of the dielectric material. This reduction brings with it increased susceptibility to higher leakage currents between the plates of the capacitor which in turn leads to a limitation on the voltage which can be applied across the capacitor. Since the charge stored is equal to the voltage across the capacitance times the capacitance, a reduction in the applied voltage requires a further increase in the capacitance in order to store the same charge, further aggravating the problem. The ability to store charge is then a function of either the thickness of the dielectric or the dielectric constant or the resistance to leakage current of the dielectric or the surface area of the capacitance.
Where silicon dioxide is the dielectric material, ultra thin dielectrics are difficult to fabricate, as these dielectric films are particularly susceptible to pin holes and other defects. Furthermore, these films are prone to high leakage currents and complete breakdown of the dielectric barrier region if high voltages are placed across the capacitor.
A common technique to increase the dielectric constant of a capacitor is to increase the dielectric constant of the capacitor from that of pure silicon dioxide.
Another technique is to decrease the leakage current between the plates of the capacitor. Different types of dielectric materials (SiO2, Si3N4, Ta2O5) sandwiched between the two electrodes of a capacitor can result in the reduction of leakage current between the capacitor plates but this reduction is of limited extent. Additional methods and techniques are therefore needed to further reduce the leakage current.
FIG. 1 provides an overview of a typical DRAM cell and its sub-components. The DRAM structure is formed on the surface of a semiconductor substrate 10. The formation of the DRAM cell starts with the isolation of the active area of the DRAM by means of the layer 12 of LOCOS or STI that is formed around the active area. A layer of Field Oxide (FOX) is also typically used for this purpose; the isolating layer of oxide is a relatively thick layer of oxide between about 2000 and 3000 Angstrom. For the silicon substrate, typically a P-type single crystal with a crystalographic orientation of (100) is used. A thin (about 100 Angstrom thick) layer of gate oxide (not shown) is grown over the silicon surface to serve as stress release. A layer 14 of polysilicon is blanket deposited over which a layer of insulating material (not shown) is deposited. These two layers are patterned and etched to form gates 14 within the active area of the device and gates 18 on the surface of the LOCOS insulating area of the device. Gates 14 in the active area of the device form the gates of the MOSFET device, gates 18 form the word lines that connect the MOSFET gates to the peripheral circuits that are connected to the DRAM chip. The Lightly Doped (LDD) regions 20 and 22 for the source/drain regions of the N-channel MOSFET are then formed, typically by implant of an N-type dopant such as arsenic or phosphorous. Next the gate spacers 16 are formed over the surface of the patterned polysilicon gates 14 and 18. These spacers are typically formed by blanket depositing of a layer of low temperature silicon oxide and etching this layer anisotropically to the surface of the substrate. The source 24 and drain 26 regions are formed by implant with an N-type dopant, for instance phosphorous. The bit line 28 to the gate of the MOSFET device is formed by conventional methods of lithography and patterning. The storage node self-aligned contact points 29 are made in a similar manner. One (or more) layers 30 of insulation are then deposited over the structure to provide protection during further processing steps. The insulating layer may contain silicon oxide or silicon nitride. Over the insulating layer a further layer of dielectric may be deposited.
The invention specifically addresses problems of measuring leakage currents that are encountered in typical DRAM structures. During conventional methods of measuring leakage current, the following problems are typically encountered:
problems introduced by background noise and the leakage current induced by background noise. While performing leakage current measurements, background noise cannot be eliminated. The relative value of the induced leakage current due to background noise increases with decreasing device feature sizes (smaller and smaller junction leakage) that is being implemented in DRAM devices of reduced size
the large number of contacts that are required in order to minimize the weighting factor of the background noise and the induced leakage current
a trade-off must be made between the area that is or can be contacted to make measurements and the required accuracy of the measurement of the leakage current
diffusion junction leakage and the contact formation leakage cannot be separately identified. Increased demands produced by improved Self-Aligned Contact (SAC) structures and processes require that an accurate method is available to identify individual sources of leakage currents and their contribution to the measured overall leakage current. This is required to for instance distinguish between leakage current that can be attributed to the diffusion process (diffusion junction) or the SAC process.
In view of the above indicated problems that are encountered with conventional methods of measuring DRAM device leakage currents, the invention provides new test structures and a new test methodology to measure these leakage currents.
A principle objective of the invention is to measure junction leakage currents for the DRAM cell storage capacitor and the bit-line node junction with an accuracy of measurement of between about 10xe2x88x9215 and 10xe2x88x9217 Amperes per contact junction at high temperatures, that is between about 85 and 125 degrees C.
Another objective of the invention is to eliminate inaccuracies that are introduced in measuring leakage current due to background noise.
Yet another objective of the invention is to reduce that large number of contacts that are required for conventional leakage current measurements.
A still further objective of the invention is to optimize the weighing factor that is required for leakage current that is introduced by background noise.
It is still another objective of the invention to eliminate the need for a trade-off between area contacted and the accuracy of the measurement in measuring leakage currents in DRAM devices.
It is still another objective of the invention to be able to clearly distinguish between the different sources and contributors of leakage currents in DRAM devices.
It is still another objective of the invention to be able to distinguish between diffusion junction leakage current and leakage current caused by contact formation.
In accordance with the objectives of the invention a new method and methodology is provided for measuring ultra-low leakage current in DRAM devices. The invention provides a method and test structures that are not limited to a trade-off between the number of contact points that are established to do the measurement and test accuracy, that can distinguish between diffusion junction leakage and leakage induced by contact regions and that can measure leakage current during on/off states of the word-line of a DRAM device.